Journal Articles
2022
[1] Mojtaba Valinataj, Axel Jantsch, "Hierarchical multipliers: A framework for high-speed multiple error detecting architectures", MICROELECTRONICS JOURNAL, 125 : 105459 - , 2022.

2021
[2] Maytham Allahi roodpoushti, Mojtaba Valinataj, "High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic", INTEGRATION-THE VLSI JOURNAL, 79 : 61 - 72, 2021.
[3] Mojtaba Valinataj, Zahra Yazdanian amiri, "Comments on "Improved designs of digit-by-digit decimal multiplier"", INTEGRATION-THE VLSI JOURNAL, 76 : 135 - 138, 2021.
[4] Mojtaba Valinataj, "An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder", International Journal of Engineering, 34 : 433 - 442, 2021.

2019
[5] Sajjad Rostami Sani, Mojtaba Valinataj, Saeideh Alinezhad, "Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags", JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 28 : 1950203-1 - 1950203-25, 2019.
[6] Mojtaba Valinataj, "Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters", MICROELECTRONICS RELIABILITY, 96 : 7 - 20, 2019.
[7] Farshid Eslami Chalandar, Mojtaba Valinataj, Hamid Jazayeriy, "Reversible Logic Multipliers: Novel Low-cost Parity-Preserving Designs", International Journal of Engineering, 32 : 381 - 392, 2019.

2018
[8] Mojtaba Valinataj, Abbas Mohammadnezhad, Jari Nurmi, "A low-cost high-speed self-checking carry select adder with multiple-fault detection", MICROELECTRONICS JOURNAL, 81 : 16 - 27, 2018.
[9] Sahar Bakhtar, Hamid Jazayeriy, Mojtaba Valinataj, "aPaRT A Fast Meta-Heuristic Algorithm using Path-Relinking and Tabu Search for Allocating Machines to Operations in FJSP Problem", Inteligencia Artificial, 61 : 111 - 123, 2018.

2017
[10] Mojtaba Valinataj, "Novel parity-preserving reversible logic array multipliers", JOURNAL OF SUPERCOMPUTING, 73 : 4843 - 4867, 2017.
[11] Majid Ghaffari, Ali A. Orouji, Mojtaba Valinataj, "Triple tooth AlGaN/GaN HEMT on SiC substrate A novel structure for high-power applications", JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 71 : 1027 - 1037, 2017.
[12] Maryam Mohajer, Mojtaba Valinataj, "A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier", International Journal of Modern Education and Computer Science, 9 : 17 - 24, 2017.

2016
[13] Mojtaba Valinataj, , Hamid Jazayeriy, "Novel low-cost and fault-tolerant reversible logic adders", COMPUTERS and ELECTRICAL ENGINEERING, 53 : 56 - 72, 2016.
[14] Mojtaba Valinataj, Mostafa Shahiri Tabarestani, "A low-cost fault-tolerant and high-performance router architecture for on-chip networks", MICROPROCESSORS AND MICROSYSTEMS, 45 : 151 - 163, 2016.

2015
[15] Mojtaba Valinataj, "Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors", MICROELECTRONICS RELIABILITY, 55 : 2845 - 2857, 2015.

2014
[16] Mojtaba Valinataj, "A novel self-checking carry lookahead adder with multiple error detection/correction", MICROPROCESSORS AND MICROSYSTEMS, 38 : 1072 - 1081, 2014.
[17] Mojtaba Valinataj, "Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures", International Journal of Engineering, Transactions A: Basics, 27 : 509 - 516, 2014.

2011
[18] Mojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg, Hannu Tenhunen, "A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip", AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 65 : 630 - 640, 2011.
[19] Mojtaba Valinataj, Siamak Mohammadi, Saeed Safari, "Fault-aware and reconfigurable routing algorithms for networks-on-chip", IETE JOURNAL OF RESEARCH, 57 : 215 - 223, 2011.

2009
[20] Mojtaba Valinataj, Siamak Mohammadi, Saeed Safari, "Reliability assessment of networks-on-chip based on analytical models", Journal of Zhejiang University-SCIENCE A, 10 : 1801 - 1814, 2009.